What happens when an ouput port is connected to an unmerged signal after an "if/else" logic?

Question

Jonathan 2022-9-16

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https://ww2.mathworks.cn/matlabcentral/answers/1806470-what-happens-when-an-ouput-port-is-connected-to-an-unmerged-signal-after-an-if-else-logic

回答： Walter Roberson 2022-9-16

I've come accross examples of models with output ports connected only to the "if" side of an if/else logic without the signal being merged beforehand.

I wonder why such a model is allowed to build and if specific configuration parameters must be set to allow it.
Also, how does Simulink deal with the undetermined output at runtime (when in the "else" case of the logic, to which the output port is not connected) ? In the examples I saw, it seems that the models would just return "Nan" in that case.
And finally, I'm curious as to how this is dealt with when generating C code from such a model.