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HDL coder fpga bitstream generation issue
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HI,
I get following screen when I run step 4.3 (Build FPGA Bitstream) in HDL workflow advisor.
A screenshot is attached for reference.
It says build has started externelly but not happens after that.
Note :
vivado can be started from MATLAB window by !vivado.
NO bitstream is generated.
Kindly guide
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回答(1 个)
Bhanu Prakash
2024-5-29
Hi Rizwan,
The bitstream generation involves invoking an external shell for the third-party synthesis tool (in your case, Xilinx Vivado) to execute a TCL script. If the bistream is not generated and no external shell pops up for the same, you can try the below mentioned troubleshooting steps to resolve the issue:
You can now try running the workflow again to check if the external shell pops up and the bitstream is generated.
Hope this helps!
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