Simulation of a PLL (Phase Locking Loop) design can be sometimes difficult as well as time consuming because of the vastly different time scales involved in the design.
Please refer the following article to have a better understanding:
Also, there are certain steps one can follow to speed up the simulation of a model in general. You may go through the following links mentioned below and try to apply the steps mentioned on the model, these steps may help to improve the simulation time.