"Failed to initialize the RTIOStream library" while installing HDL Verifier Support Package for Xilinx FPGA Boards add-on

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Charles 2022-12-9

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https://ww2.mathworks.cn/matlabcentral/answers/1874922-failed-to-initialize-the-rtiostream-library-while-installing-hdl-verifier-support-package-for-xili

评论： Jestzer 2022-12-13

Hello,

This issue is different from this question - I have the issue while trying to configure the add-on. I think I'm following the steps correctly; here's my steps:

Disconnect the board from everything
Plug in the power
Plug in a micro-USB connector to the JTAG port
Turn on the power to the board
Click "Test Connection"

Note: Neither Ethernet nor the serial port USB cables are connected.

Here's the error:

What should I be doing?

Thanks,

Charles

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Charles 2022-12-10

I don't understand your suggestion. I did press "Test Connection". It took 5-10 minutes to synthesize a bitstream (I'm assuming) and then managed to program the FPGA (step 2). If I press "Test Connection" again, it will try steps 1 and 2 all over again and then fail with the same error message. Is there a log file somewhere that provides more info? That would be helpful.

Jestzer 2022-12-10

Sorry, I don't my my own board for testing, I was just going off of a similar question/issue posted here and I thought that was from the "Test Connection" button. Maybe it's from the Diagnostic Viewer, but I'm not too sure.

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Answer 1

Charles 2022-12-13

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https://ww2.mathworks.cn/matlabcentral/answers/1874922-failed-to-initialize-the-rtiostream-library-while-installing-hdl-verifier-support-package-for-xili#answer_1127017

Hi all,

The issue seems to be that the Digilent Adept 2 Runtime was not installed. See also: Supported EDA Tools and Hardware and go to the link above for instructions. My mistake was not understanding that the ZCU-102 board has this module on it.

Also, I had installed the Xilinx JTAG drivers (/opt/Xilinx/Vivado/2020.2/data/xicom/cable_drivers/lin64/install_script/install_drivers/install_drivers) on advice from co-workers. This was probably right for using the Xilinx JTAG tools, but not right for HDL Verifier.

Charles