Generating asynchronous delays with HDL coder in Simulink

2023 2 21
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更新时间：2023 2 22
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Hi,
actually VHDL language supports various methods to model asynchronous delays of signals such as "transport" "inertial" and "wait".
Unfortunately it seems that HDL coder library does not include any supported block to model this functions, I can find only the Z^-1 block.
Is there any way to emit a propagation delay of a signal in the ouput code?
Thank you

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Ryan Baird
Ryan Baird 2023-2-21

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Since transport delays, inertial delays, and wait statements are simulation-only, non-synthesized VHDL constructs that are ignored by synthesis tools and are not guaranteed to accurately reflect what will happen in hardware, HDL Coder uses some of them in testbench code to model timing but does not currently provide a way to model your own.
If you're just looking to see the signal propagation so you can see how a value was computed, whichever simulator you're using likely has a way to expand delta cycles.

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stefano
stefano 2023-2-22
编辑：stefano 2023-2-22
I'm looking for a way to quickly create VHDL models of asynchronous logic such as a digitally programmable delay lines or phase detectors with a parameterized dead band.
I am aware that delay statements in VHDL cannot be synthesized but if HDL coder had the possibility to model them, output codes could also be created for simulation test benches as well as for synthesis tools.
It would be very useful for speeding up simulations in silicon design verification flows imho where at the moment the alternative would be to either write the VHDL models by hand or use different languages like systemC that requires additional cosimulation tools.

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