Deep Learning HDL Toolbox - DE10-Standard

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回答： Vikram Venkatesh 2023-5-19
I am trying to use a DE10-Standard FPGA development kit and I use this example: https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html as a reference. I am trying to do step ,,Create the reference design definition file. To generate a deep learning processor IP core, you must define these three AXI4 Master Interfaces" but I struggle with this part of a code:
hRD.addCustomVivadoDesign( ... 'CustomBlockDesignTcl', 'system_top.tcl',... 'VivadoBoardPart', 'xilinx.com:kcu105:part0:1.0');
I know that I should use addCustomQsysDesign function that refers to Qsys project file, but I want to know what that project needs to contain. Clock, HPS, PLL and DDR memory Interface?

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回答（1 个）

Vikram Venkatesh
Vikram Venkatesh 2023-5-19
The Qsys project file must contain all modules referenced in the block diagram in this https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html, except for the deep learning processor IP core. The project file requires:
  • Clock source
  • JTAG AXI Manager Interface
  • DDR4 external memory interface
  • Hard Processor System (HPS), and
  • PLL
To learn more about creating a reference design for Intel targets, see https://mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-intel-soc-workflow.html

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