real data type from hdl coder
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Hi,
the hdl coder generates real data type which is not synthesizeable, only useful for simulation purpose.
How can we make the hdl coder to generate std_logic_vector before we convert to vhdl
thanks
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Tim McBrayer
2015-4-13
0 个投票
HDL Coder's bit true and cycle accurate output mirrors precisely what you have placed into your Simulink or MATLAB design. If your design has double or single types, they will be emitted as real in VHDL or Verilog. You will need to convert your modeled types to a non-floating point type, most likely to fixed point. For MATLAB-based designs HDL Coder has fixed-point conversion built into the product workflow. For Simulink-based designs you can use the Fixed-Point Tool to aid you in your conversion.
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