Yes, you can specify the word sizes for RISC-V using the built-in RISC-V device details in the Hardware Implementation section of the Configuration Set (as shown below.)
The C standard does not fully specify integer word sizes so this will ensure that the generated C/C++ code will have the same numerical results on the target as it had in the model simulation.
The generated algorithm code can then be integrated and plugged into your embedded software framework and scheduler as you would do with hand code for your production hardware.
If you desire complete support of a particular RISC-V Board, that is directly generated from Embedded Coder with I/O drivers, scheduler, profiling, and more, you can request MathWorks consulting services to create a custom Embedded Target solution.
