Generate root level virtual bus outport as struct

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Jake Gareau
Jake Gareau 2023-8-16
回答： Abhas 2024-12-4，9:23
I have a model that outputs a virtual bus composed of a few subordinate buses.
when I generate code, the model output is a strucutre that contains each variable located at the same hierarchy. I would like to maintain some of the strucutre of the virtual bus for organizational purposes as well as for readability of the variable name.
I have already tried using the code mappings to set the outputs as storage class 'struct' but this appears do nothing for a virtual bus
The main reason I do not want to use a nonvirtual bus, is I do not wish to maintain the data type inside of my datadictionary. If SubBus1 changes for example then that change is automatically reflected elsewhere and I do not need to update the bus definitions.
Here is what I am looking to achieve with the codeGen with virtual bus vs what I get
My output is a virtual bus ExtY which is composed of SubBus1, SubBus2.... etc
I would like to see this in the code as:
typedef struct {
SubBus1_T SubBus1;
SubBus2_T SubBus2;
} ExtY_ModelName_T;
in the generated code I end up with ExtY_ModelName which has varaibles
typedef struct {
real32_T ExtY_SubBus1_Var1;
real32_T ExtY_SubBus1_Var2;
real32_T ExtY_SubBus2_Var1;
real32_T ExtY_SubBus2_Var2;
} ExtY_ModelName_T;

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回答（2 个）

Ruchika
Ruchika 2023-8-17
Hi, to achieve the desired code generation with a virtual bus, you can use structure padding and code replacement techniques. Here's how you can implement it:
1. Create a 'Simulink.Bus' object in your Simulink model to represent the virtual bus. Add the necessary signals and sub-buses as elements of the virtual bus.
2. In the Data Dictionary, create a structure type definition for each sub-bus (`SubBus1_T`, `SubBus2_T`, etc.) and define the variables inside each sub-bus.
3. Create a structure type definition for the virtual bus (`ExtY_ModelName_T`) and include the sub-bus types as elements of the virtual bus type.
4. In the Code Mappings editor, set the storage class of the virtual bus output (`ExtY`) to `struct` and specify the structure type as `ExtY_ModelName_T`. This will ensure that the generated code uses the structure type for the virtual bus.
5. In the Code Mappings editor, define code replacements to rename the individual variables inside the virtual bus to match the desired naming convention. For example, replace `ExtY_SubBus1_Var1` with `SubBus1.SubBus1_Var1`, and so on.
By following these steps, the generated code should reflect the desired structure and variable names for the virtual bus.
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Jake Gareau
Jake Gareau 2023-9-6
is it possible to automatically create the 'Simulink.Bus' object based upon the existing virtual bus?
for a larger bus with several sub busses it would be a bit tedious to create all these definitions.

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Abhas
Abhas 2024-12-4，9:23
Hi @Jake Gareau,
To programmatically create "Simulink.Bus" objects for virtual buses to preserve their hierarchy during code generation without manually defining each bus we can use the below example code:
% Create Simulink.Bus objects automatically for the virtual bus
blockPath = 'YourModelName/YourBlockPath'; % Replace with your model/block path
outputPortHandle = get_param(blockPath, 'PortHandles');
outputSignal = get_param(outputPortHandle.Outport(1), 'SignalHierarchy');
% Recursively create bus objects
Simulink.Bus.createObject(outputSignal);
After creating the bus objects, ensure the code mappings are properly configured:
  • Use "Signal Attributes" block settings or set the storage class explicitly to ensure the bus hierarchy is preserved:
  • Go to "Model Configuration Parameters" → "Code Generation" → "Interface".
  • Under the "Root-Level Outports" tab, map the output port to a storage class like "ExportedGlobal".
  • Verify that the hierarchical structure of the bus is preserved in the code generation configuration by selecting "Preserve Names of Model Block I/O Variables" under "Code Generation" > "Identifiers".
  • The generated code will maintain the desired structure like the below:
typedef struct {
SubBus1_T SubBus1;
SubBus2_T SubBus2;
} ExtY_ModelName_T;
You may refer to the below documentation links to know more about the same:
  1. https://www.mathworks.com/help/simulink/slref/simulink.bus.createobject.html
  2. https://www.mathworks.com/help/ecoder/ug/configure-outport-blocks-for-c-code-generation.html
I hope this helps!

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