How can I add a finish signal for HDL generation?

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King 2015-4-16

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https://ww2.mathworks.cn/matlabcentral/answers/203932-how-can-i-add-a-finish-signal-for-hdl-generation

评论： Bharath Venkataraman 2015-6-11

I created a algrithm using simulink and used HDL Coder to have my VHDL code generated. But I found that there's no flag indicate that the ouput result is already at the output port, I wonder if there's any way to solve this question? Any help would be appreciated. Thanks.

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Answer 1

Bharath Venkataraman 2015-4-16

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If you are referring to the latency of the system due to registers in the path between input and output, a valid flag is typically modeled as an output of the design to indicate that data is ready.

This valid flag in the Simulink simulation should go high when the data is ready on the output. Once you verify this working in your Simulink design, you can generate HDL code for it and you will find the same valid output available in HDL as well.