FIL I/O options missing in the FIL wizard.
2 次查看(过去 30 天)
显示 更早的评论
Hi, I am using MATLAB R2022b and Vivado 2020.2. I am trying to put the Zynq (xc7z020-2clg400) board as FPGA-in-the-loop in Simulink. And I noticed- when opening FIL wizard, FIL I/O is missing. I do not know why this is happening and it will be helpful if someone can put some light on it. I have attached the figure below where the FIL I/O missing are highlighted.
0 个评论
回答(1 个)
Tom Richter
2023-11-16
Hi Charanraj,
I assume you refer to the FIL I/O panel in the FPGA Board Wizard of the FPGA Board Manager. You can access the FPGA Board Manager by clicking on Launch Board Manager in the FIL Wizard.
Best regards,
Tom
3 个评论
Tom Richter
2023-11-24
Hi Charanraj,
sorry for the delay. I checked your steps and now have an answer. You selected a Zynq device. For Zynq we do not support direrect ethernet (ethernet can be used via PS and LibIIO driver for FIL).
When you select e.g. Artix7 you will get this:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1551302/image.png)
and on the next page this:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1551307/image.png)
You can see that the FIL I/O is only related to ethernet port settings not JTAG. So you did nothing wrong and it should work.
Best regards,
Tom
另请参阅
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!