- In Xilinx Vivado, generate a testbench for the IP core. This testbench should include the necessary stimuli and any additional logic required to interact with the IP core.
- Now, export the testbench generated in Vivado as VHDL or Verilog files.
About Xilinx Vivado ip core, How do I verify ip cores using FPGA-in-the-loop.
3 次查看(过去 30 天)
显示 更早的评论
I used Xilinx Vivado ip core in my project, now I would like to verify this project using the simulink. But in the FPGA-in-the-Loop Wizard Sources Files windows, I only add .v or .vhdl sources files. How to solve it? Please
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1543152/image.png)
0 个评论
采纳的回答
Tushar Sharma
2023-11-27
Hi,
I understand that you want to verify your project using Simulink, but you are unable to add the source files in the "FPGA-in-the-Loop Wizard" window as it only accepts VHDL or Verilog files.
To interface Xilinx Vivado IP cores with Simulink for verification, you can follow these steps:
These exported files can now be used for verification as sources for simulation in Simulink.
Hope it helps!
Best regards,
Tushar Sharma
更多回答(0 个)
另请参阅
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!