Hi BUMHEE,
I understand that you're trying to use Vitis firmware to control the hardware, what is the issue that you're facing while using the firmware. Can you try the following.
- Verify the Generated Interface: Ensure that the host computer interface generated by MATLAB (gs_hdlcoder_scale_amplitude_interface.m) matches the interface expected by the VITIS firmware. The interface should correctly handle communication with the FPGA, including data frames and register access.
- Confirm Setup Function Configuration: The setup function (gs_hdlcoder_scale_amplitude_setup.m) configures the FPGA hardware object with the correct ports and interfaces, as defined in the Set Target Interface task. Double-check that the VITIS firmware reflects these configurations accurately, particularly the memory-mapped registers and DMA settings.
- Functionality Equivalence: The MATLAB script (hdlcoder_scale_amplitude_script.mlx) provides a live demonstration of interacting with the FPGA design. Ensure that the equivalent functionality is correctly implemented in the C/C++ code in VITIS. This includes writing to AXI registers and managing data frames for input and output signals.
- Use VITIS Debugging Tools: If the firmware isn't behaving as expected, utilize the debugging tools available in VITIS to step through the code and monitor the FPGA's behavior. Check that the C/C++ code is correctly initiating DMA transfers, writing to AXI4-Lite registers, and managing data streaming.
- Review MATLAB Generated Files: The files generated from the MATLAB example can provide insight into how MATLAB scripts interface with the FPGA hardware. Use these as a reference to ensure that the VITIS firmware performs equivalent operations.
- Resource Management: Ensure that the VITIS firmware includes proper resource management, releasing any allocated resources after execution to avoid issues on subsequent runs, similar to the release(hFPGA); command in MATLAB.
You should be able to figure out the issue and resolve with this.
