Hello,
I make project with FPGA and I use Data Capture from extension HDL Verifier. I use FPGA Digilent Arty S7-25 and Digilent JTAG HS1. I need continuously transfer about 20Mbit audio data every second from FPGA to Matlab. Now I have created project according to the example "Stream Audio Signal from Intel FPGA Board Using Ready-to-Capture Signal" and JTAG freqvency is set to 30MHz. The problem is that even then it is not possible to transfer data to the computer at such a speed and this will cause FIFO memory overflow and data loss. I have simple Matlab code with step() function and for-cycle for repeated function call. I tried to measure the execution time of step() and one step() takes about 250ms, but I need call step() much faster. Are there some settings for Data Capture transfer speed or setting the speed of the step() function call or it is not possible to transfer data from FPGA to Matlab at such a speed?
Thanks for the reply.
