How to Resolve Port Widths/Dimensions Mismatch Error in Simulink Model During Surrogate Optimization ?

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Shardul
Shardul 2023-11-25
编辑： Arka 2023-12-26
I am currently facing an issue with a surrogate optimization process in MATLAB, using a Simulink model named 'ConfiguredVirtualVehicleModel'. The process involves running a function 'RunEV', which simulates electric vehicle (EV) performance under various conditions. However, I encounter a specific error during the simulation build process, particularly related to the dimensions of input and output ports in the 'BMSController' subsystem.
The error messages are as follows:
  1. "Error in port widths or dimensions. 'Output Port 1' of 'BMSController/RT' is a one-dimensional vector with 80 elements."
  2. "Error in port widths or dimensions. 'Input Port 2' of 'BMSController/Balancing Logic' is a one-dimensional vector with 100 elements."
This mismatch in port dimensions is causing the build procedure for the 'BMSController' to abort. I'm seeking advice on how to effectively resolve this port dimensions mismatch issue within the Simulink model to ensure successful execution of the surrogate optimization process. Any guidance on specific steps or strategies to diagnose and fix this discrepancy in port sizes would be greatly appreciated.
  1 个评论
madhan ravi
madhan ravi 2023-11-25
you probably should share a picture or model so that it is easier for others to understand the problem. is the outport of RT subsytem connecting to inport of Balancing logic subsystem? and are you doing some calculations inbetween them?Again without seeing your model it's hard to guess.

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回答（1 个）

Arka
Arka 2023-12-26
编辑：Arka 2023-12-26
Hi @Shardul,
I understand you are facing an issue with inconsistent block dimensions in a subsystem in your model.
It is difficult to provide a conclusive answer without taking a look at your model, but here are some steps which might help you resolve this issue:
  1. Identify the mismatched ports in the "BMSController" subsystem.
  2. Check for Block Parameters (to which the inports and outports are connected) and see if there are any settings which define the port dimensions
  3. Examine upstream blocks (ones feeding into "RT" and "Balancing Logic") to see if dimensions are defined there.
Hope this helps.

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