IP core generation for built-in Simulink model

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Alex Alex
Alex Alex 2024-2-6
编辑： Alex Alex 2024-3-3
I want to generate HDL code (IP core) for my model that consists of the Channelizer block.
My model has the following inputs:
data_input (sfix12, complex), valid_input (boolean).
My model has the following outputs:
data_output (sfix12_E3 [1x30], complex), valid_output (boolean).
The problem is that I am unable to generate IP core for my model. I have tried dozens of configurations but different errors occurs.
Questions:
  1. Do I need to use frame to sample conversion in my case (considersing output is a complex vector)?
  2. How AXI4 interface will be generated for valid_input input? Will the signal reach the Channelizer block within one clock cycle (or signal will control only AXI interface)?
If the answer for the question #1 is yes then I get the following errors:
  1. When frame to sample conversion is enabled, streamed scalar ports are not supported (if convertToSamples for ports are on).
  2. When frame to sample conversion is enabled, interface 'AXI4-Stream Slave' can only be assigned to streamed ports (if convertToSamples for ports are off).
If the answer for the question #1 is no then I get the following error:
Using AXI4-Stream interface with Ready port unassigned is not supported when "Minimize clock enables" is in effect (although TREADY port is not listed in the Interface Mapping options).

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回答（2 个）

Kiran Kintali
Kiran Kintali 2024-2-7
Please share your model if possible. I am attaching few sample design patterns that show how to build HDL Coder compliant design.
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Alex Alex
Alex Alex 2024-2-7
My model is just from this example:
https://www.mathworks.com/help/dsphdl/gs/generate-hdl-code-for-high-throughput-channelizer.html

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Kiran Kintali
Kiran Kintali 2024-2-14
Unfortunately we do not have your contact in our tech support database. Can you reach out to our support team via email to support@mathworks.com or create a tech support ticket https://www.mathworks.com/support/contact_us.html?
My model has the following inputs: data_input (sfix12, complex), valid_input (boolean).
My model has the following outputs: data_output (sfix12_E3 [1x30], complex), valid_output (boolean).
We need few additional details such as what is the FFT size / FFT length that you are expecting to use within the HDL DUT?

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