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Kiran Kintali


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MathWorks

254 total contributions since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

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Answered
Timed out on waiting for AXI write response.
This is insufficient info to answer the question. Someone to answer this question would need to know the following details at th...

2 hours ago | 0

Answered
HDL Coder Sharing alters wordlength of multiplier
In hardware multipliying two inputs of size 'n' and 'm' would result in full precision output of 'n+m'. The result is further tr...

19 hours ago | 0

Answered
HDL FIFO and (not so) algebraic loop errors
Can you share the model with the algberaic loop error? What version of MATLAB and HDL Coder are you currently using? Thanks.

19 hours ago | 1

Answered
from HDL to Matlab
You can consider using HDL cosimulation block in Simulink. https://www.mathworks.com/help/hdlcoder/ug/hdl-verifier-cosimulation...

6 days ago | 0

Answered
Generate HDL error: Reference to non-existent field 'hasVariantError'.
Thanks for reporting this issue. An updated check compatibility of the Simulink code generation folder is added during HDL code ...

6 days ago | 1

Answered
Custom Convolution neural network model code conversion for FPGA
https://www.mathworks.com/products/deep-learning-hdl.html Deep Learning HDL Toolbox™ provides functions and tools to prototype ...

6 days ago | 0

Answered
State vector PWM on FPGA
Can you check if these links are of help? Deploy Simscape Buck Converter Model to Speedgoat IO Module Using HDL Workflow Script...

7 days ago | 0

Answered
HDL coder and verifier: Xilinx Arty S7-25 vs S7-50
The generated HDL code from HDL Coder and HDL Verifier workflows are not tied to specific hardware and wide range of FPGA device...

13 days ago | 1

Answered
Can anyone help me with the name of this block?
web(fullfile(docroot, 'simulink/slref/ratetransition.html')) NoOp --> Does nothing / Copy

19 days ago | 0

Answered
How to integrate with Verilog Code Generator with custome approach instead of Simulink?
web(fullfile(docroot, 'hdlcoder/gs/generate-hdl-code-from-matlab-code-using-the-command-line-interface.html')) This product hel...

20 days ago | 0

Answered
How to integrate with Verilog Code Generator with custome approach instead of Simulink?
Here are some links that can help in describing the workflow to translate MATLAB to Verilog. Please note you need to follow best...

20 days ago | 0

Answered
fixdt in simulink and fixed-point percision in system generator is equal ???
This should help answer the question on proper use of Xilinx System Generator and HDL Coder in an integrated workflow. https://...

25 days ago | 0

Answered
HDL generation from inside a (library) linked subsystem
HDL code generation from reference subsystems is now supported in HDL Coder.

25 days ago | 0

Answered
How to remove errors of Verify Fixed Point Design step of HDL Coder?
Fixed-point conversion is an assisted process. Automated conversion of fixed-point can fail if best practices of conversion are ...

25 days ago | 0

Answered
how to use an external memory(ddr2, dpram) in HDL coder by matlab??
Performing Large Matrix Operation on FPGA using External Memory web(fullfile(docroot, 'hdlcoder/ug/performing-large-matrix-oper...

25 days ago | 0

Answered
how does loop unroll work in hdl coder?
These HDL Coder documentation files should explain the behavior. https://www.mathworks.com/help/hdlcoder/ref/coder.hdl.loopspec...

25 days ago | 0

Answered
How to solve "unsupported unbounded loop structure" error when generate hdl code from stateflow
The model has only dead logic. Please share updated model.

25 days ago | 0

Answered
How to implement a 3D Lookup Table that can be converted with HDL Coder?
Can you consider the following modeling workaround until 3D LUT table support is available in HDL Coder?

27 days ago | 0

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Answered
How to implement a 3D Lookup Table that can be converted with HDL Coder?
3D LUT support is on the HDL Coder near term product roadmap and will be available in an upcoming release. In the interim we ca...

28 days ago | 0

Answered
HDL Coder failing for single-precision
Thank you for reporting this error. This is unexpected. Can you share a reproduction model? It will help verify this issue is ...

1 month ago | 0

| accepted

Answered
Error in HDL Coder- Fixed point conversion "MATLAB expression 'r' is not of the correct class: expected 'double', found 'sym'."
You may want to check how to code this algorithm to be compatible with HDL Coder and FPGA Modeling Guidelines. There are some go...

1 month ago | 0

Answered
is modelsim 10.7 is compitable with hdl verifier 2020a?
https://www.mathworks.com/help/hdlverifier/gs/supported-eda-tools.html Please check Mentor Graphics Questa and ModelSim Usage R...

1 month ago | 0

Answered
HDL Coder RAM mapping failed
HDL Coder would need input types to infer the intermediate and output types. Please specify in = <sample value>; % define in...

1 month ago | 0

Answered
How to resolve the exceed of maximum supported wordlength of 128 bits in hdlcoder?
HDL Coder supports various data types for synthesis. If you need high dynamic range in computation you need to use native floati...

1 month ago | 0

Answered
problem generating hdl ip core of statflow using hdl workflow advisor: can't run the 1.2 task Set Target Reference Design
Unfortunately the attached model does not compile. Can you send updated instructions? === Update Diagram (Elapsed: 0.522 sec) =...

1 month ago | 0

Answered
xmakefilesetup configuration for Xilinx software
HDLCoder works in conjuction with System Generator. See example here. https://www.mathworks.com/help/hdlcoder/examples/using-xi...

1 month ago | 0

Answered
Eliminating algebraic loops with the Induction motor simulation
For HDL code generation the model first needs to be discretized (use z^-1 blocks). Attached is an example model with flux equat...

1 month ago | 0

Answered
Why does Image Filter does not produce valid output when using certain image dimension?
Can you share a sample model that reproduces the issue? Thanks This is another example shows how to design a hardware-targeted ...

1 month ago | 1

| accepted

Answered
error while programming hardware :device arm dap_1 is not programmable
Per release notes this feature is available in R2020a release. https://www.mathworks.com/help/hdlverifier/release-notes.html ...

1 month ago | 0

| accepted

Answered
How to use the fixed-point designer properly - several issues.
Sure. Could you share sample models?

1 month ago | 0

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