I am currently working on an ASIC design project and have both HDL Coder and the Deep Learning HDL Toolbox installed. I need to generate Verilog code that can be simulated in Synopsys VCS or Siemens Questa, rather than creating a bitstream for FPGAs using tools like Vivado or Quartus.
The documentation for the Deep Learning HDL Toolbox states that it "enables you to customize the hardware implementation of your deep learning network and generate portable, synthesizable Verilog and VHDL code for deployment on any FPGA or SoC (with HDL Coder and Simulink)." However, I have only found documentation related to FPGA development and haven’t come across resources specifically focused on generating Verilog code for ASIC design.
Has anyone successfully used these tools for ASIC-focused Verilog generation and simulation? If so, could you point me to any documentation or examples that cover this workflow? Alternatively, if this isn’t supported, is there a workaround or another tool that might help bridge the gap?
For example, for a MATLAB built-in pretrained image classification network like SqueezeNet:
[net, classNames] = imagePretrainedNetwork("squeezenet");
What are the next steps to generate an int8 quantification Verilog top module with a matrix (227 x 227 x 3) input [7:0], and 1000 output [7:0]?
Any guidance would be greatly appreciated!
