Simulink HDL Coder error when generating

Question

0 个投票

HEllo,

It is my first time with Simulink's HDL Coder and I am trying to code a very simple program.

I have it ready, it simulates correctly but when I hit Generate HDL Code, it gives me this error:

Error:Error:signal:addDriver:invalidOutPortIndex: Error: Invalid output port index 3, hdl_test" RefNum="c31" UserName="If" RTTIClass ="class pir::NetworkInstComp" Network="n1"/> has 3 output port(s)

It is a simple counter that outputs 8 bits to toggle corresponding leds.

Can anyone give me some light on what can it be happening??

Thanks!!

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Steven Hatcher 2025-2-20

编辑：Steven Hatcher 2025-2-20

Hi Mikel,

Which release are you using? It will be helpful to reach out to technical support to help get the issue sorted out.

Can I ask what you are trying to do with this If Action Subsystem structure? It almost looks like lookup table logic if those are constants inside. If so, you can get much more efficient HDL code using the nD Lookup Table block and also reduce modeling overhead with a single block.

Steven

Mikel 2025-2-20

编辑：Mikel 2025-2-20

在 MATLAB Online 中打开

I am using MAtlab R2023b

I am trying to implement a binary counter that, depending on the value of it, will turn on-off 8 leds.

the equivalent VHDL code would be:

MAIN: process(rst,clk)
    begin
    
        if (rst = '1') then
            count <= (OTHERS => '0');
            leds <= (OTHERS => '0');
        elsif rising_edge(clk) then
            count <= std_logic_vector(to_unsigned(to_integer(unsigned(count))+1,count'length));
            if to_integer(unsigned(count)) <= 500000 then
                leds <= std_logic_vector(to_unsigned(1,leds'length));
            elsif to_integer(unsigned(count)) <= 1000000 then
                leds <= std_logic_vector(to_unsigned(2,leds'length));
            elsif to_integer(unsigned(count)) <= 1500000 then
                leds <= std_logic_vector(to_unsigned(4,leds'length));
            elsif to_integer(unsigned(count)) <= 2000000 then
                leds <= std_logic_vector(to_unsigned(8,leds'length));
            elsif to_integer(unsigned(count)) <= 2500000 then
                leds <= std_logic_vector(to_unsigned(16,leds'length));
            elsif to_integer(unsigned(count)) <= 3000000 then
                leds <= std_logic_vector(to_unsigned(32,leds'length));
            elsif to_integer(unsigned(count)) <= 3500000 then
                leds <= std_logic_vector(to_unsigned(64,leds'length));
            elsif to_integer(unsigned(count)) <= 4000000 then
                leds <= std_logic_vector(to_unsigned(128,leds'length));
            else
                count <= (OTHERS => '0');
                leds <= (OTHERS => '0');
            end if;
        end if;
    
    end process MAIN;

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Answer 1

Kiran Kintali 2025-2-20

0 个投票

This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We will provide a workaround and a patch as soon once we diagnose the issue.

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Steven Hatcher 2025-2-20

在 MATLAB Online 中打开

Thanks for sharing the model.

It appears to be a bug when using multiple elseif expressions. I was able to make the fix already.

But this will not generate very efficient code if all you are doing in the action subsystems is passing out a constant. There's better ways to create this mapping logic. You can easily use a MATLAB Function block to do this, which even allows the use of binary and hex literals.

function leds = fcn(count)

if count <= 500000

leds = 0b00000001;

elseif count <= 1000000

leds = 0b00000010;

elseif count <= 1500000

leds = 0b00000100;

elseif count <= 2000000

leds = 0b00001000;

elseif count <= 2500000

leds = 0b00010000;

elseif count <= 3000000

leds = 0b00100000;

elseif count <= 3500000

leds = 0b01000000;

elseif count <= 4000000

leds = 0b10000000;

else

leds = 0b00000000;

end

The generated VHDL code for this also looks similar to the style of logic you were looking for with if-elseif usage.

  MATLAB_Function_1_output : PROCESS (count_unsigned)
  BEGIN
    IF count_unsigned <= to_unsigned(16#0007A120#, 32) THEN 
      leds_tmp <= to_unsigned(16#01#, 8);
    ELSIF count_unsigned <= to_unsigned(16#000F4240#, 32) THEN 
      leds_tmp <= to_unsigned(16#02#, 8);
    ELSIF count_unsigned <= to_unsigned(16#0016E360#, 32) THEN 
      leds_tmp <= to_unsigned(16#04#, 8);
    ELSIF count_unsigned <= to_unsigned(16#001E8480#, 32) THEN 
      leds_tmp <= to_unsigned(16#08#, 8);
    ELSIF count_unsigned <= to_unsigned(16#002625A0#, 32) THEN 
      leds_tmp <= to_unsigned(16#10#, 8);
    ELSIF count_unsigned <= to_unsigned(16#002DC6C0#, 32) THEN 
      leds_tmp <= to_unsigned(16#20#, 8);
    ELSIF count_unsigned <= to_unsigned(16#003567E0#, 32) THEN 
      leds_tmp <= to_unsigned(16#40#, 8);
    ELSIF count_unsigned <= to_unsigned(16#003D0900#, 32) THEN 
      leds_tmp <= to_unsigned(16#80#, 8);
    ELSE 
      leds_tmp <= to_unsigned(16#00#, 8);
    END IF;
  END PROCESS MATLAB_Function_1_output; 

Kiran Kintali 2025-2-21

We are addressing the issue with the if-elseif blocks and will release an update patch shortly. For control structures such as if/elseif and switch/case, we recommend using the MATLAB function block. This approach enhances model readability and clarifies control logic. Nonetheless, we also fully support the Simulink representations, as it explicitly illustrates both the data flow and control flow.

Please note that HDL Coder unifies all these modeling/representations internally prior to code generation and attempts to optimizes the logic across those constructs. Ideally users should use what works best for them in terms of representing math in MATLAB, Simulink, Stateflow and Simscape.

We will see what else can be done to improve the nD-lookup support. This page has some guidance on best practices using LUT blocks

https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-ram-and-rom-in-simulink.html

Steven Hatcher 2025-3-6

We've published a bug report on this issue. You can track when the fix gets ported to updates for older releases with it.

https://www.mathworks.com/support/bugreports/3567496

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