已回答
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...

8 months 前 | 1

已回答
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...

8 months 前 | 0

| 已接受

已回答
Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...

8 months 前 | 0

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Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...

8 months 前 | 0

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Deep Learning HDL Toolbox with CycloneV SoC board
Can you consider using the example and extend to DE-10 Nao Kit? https://www.mathworks.com/help/hdlcoder/ug/define-and-register-...

8 months 前 | 0

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Convert a part of simulink model of my project to VHDL or Verilog code for FPGA
https://www.mathworks.com/help/hdlcoder/simscape-to-hdl.html Simscape Hardware-in-the-Loop Workflow Generate HDL code from S...

10 months 前 | 0

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Is it possible to change Simulink MATLAB Function Block 1-indexing to 0-indexing?
If possible can you share your model and the version of MATLAB you are using? There are few tricks in MATLAB coding and design...

11 months 前 | 0

| 已接受

已回答
Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？
HDL Coder Language Support VHDL, Verilog, and SystemC HLS Language Support The generated HDL code complies with the following...

11 months 前 | 1

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When I click on "View Code" after generating Verilog code in HDL Coder, the program doesn't respond.
https://www.mathworks.com/help/hdlcoder/ug/traceability-report.html If you are facing issues with code view please reach out to...

11 months 前 | 0

| 已接受

已回答
HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing
If the generated HDL DUT code results in unreasonable IO, it may eventually lead to failure to meet pin constraint during synthe...

11 months 前 | 0

已回答
SigmoidLayer wont work while implementing on ZC706
Thank you for reporting this. Development team is able to reproduce the issue and will post an update soon.

11 months 前 | 0

已回答
Simulink HDL Coder error when generating
This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We ...

12 months 前 | 0

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How can we tune the Discrete integrator of the HDL Coder for second order generalized integrator for FPGA
Can you share the model here or via tech support? Thanks

12 months 前 | 0

| 已接受

已回答
Can't register a custom board for the HDL Deep Learning Toolbox
>> Does MATLAB have the option to register a custom board? Yes, You can see the doc here https://www.mathworks.com/help/hdlcode...

12 months 前 | 0

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How do I configure HDL Coder so that it recognizes my Vivado version?
Please review this post that is relevant here. https://in.mathworks.com/matlabcentral/answers/518421-which-versions-of-vivado-a...

12 months 前 | 0

| 已接受

已回答
What's the most suitable Vivado version for Matlab 2025a
This example shows how to model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal d...

12 months 前 | 0

| 已接受

已回答
MATLAB HDL-Coder: Expression could not be reduced to a constant.
Is hwconst an input variable (creates hardware interface pins) or just a non-tuanble constant parameter passed into the design...

12 months 前 | 0

| 已接受

已回答
Troubleshooting Signal Logging in SDI for FPGA Outputs in Speedgoat Motion Control HDL I/O Blockset
Klemen, Thanks for reporting this. Our support team at Speedgoat is reviewing the issue and respond here shortly.

1 year 前 | 1

已回答
How to resolve unsupported functions in MATLAB HDL Coder?
Happy to assist you with your MATLAB to HDL workflow. Attached is a sample zip file with the code for the attached functions (us...

1 year 前 | 0

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Error evaluating parameter. Dot indexing is not supported for variables of this type.
Can you please share your model here or reach out to tech support? The following message is not expected and a better message ne...

1 year 前 | 0

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Matlab for my needs
https://www.mathworks.com/help/hdlcoder/examples.html https://www.mathworks.com/help/hdlcoder/run-and-verify-generated-ip-cor...

1 year 前 | 0

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Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project?
Generating an IP core wrapper for the HDL Coder generated code is the best way to integrate your algorithm into an existing vi...

1 year 前 | 1

已回答
Ultra RAM on True Dual Port RAM
Please do attach your sample model as a test case. This is a known issue and HDL Coder R&D team have reported the issue to Viva...

1 year 前 | 0

| 已接受

已回答
Using fixed FPGA capacity for a variable number of Simulink signal channels
Have you considered tunable parameter usage in HDL Coder? https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-...

1 year 前 | 0

已回答
HDL Coder "Error using find Too many input arguments."
Based on the error message this issues seems to be related to report generation infrastructure failure. The issue is resolved in...

1 year 前 | 0

已回答
Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?
Please share your release. Adaptive Pipelining is an optional feature. When enabled it tries to improve timing of your design. ...

1 year 前 | 0

已回答
Deep Learning HDL Toolbox + Quartus Pro 23.3
Please check the HDL Coder supported version of Intel Quartus with R2024a and R2024b releases. https://www.mathworks.com/help/r...

1 year 前 | 0

已回答
how to download the third party support package file "xilinx linux binaries"
What version of MATLAB are you using? Please do not hesitate to reach out to tech support.

1 year 前 | 0

已回答
Seeking Guidance on Auto-Generating Verilog Code for ASIC Simulation with HDL Coder and Deep Learning HDL Toolbox
Classify ECG Signals Using DAG Network Deployed to FPGA This example shows how to classify human electrocardiogram (ECG) signal...

1 year 前 | 0

已回答
Characterisation error in HDL code generation?
This is an unexpected error. What version of MATLAB are you using? Can you share the model? Do not hesitate to reach out to te...

1 year 前 | 0