Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?

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xiaodong yu
xiaodong yu 2024-11-19，10:06
评论： Steven Hatcher 2024-11-20，17:08
Hi,
I want to use adaptive pipeline to optimize the multiply-add module in HDL coder for xilinx FPGA. I enable adaptive pipline for a sub module. It added additional delay (pipline register to the design) to the data path but simulation on the design do not reflect the delay. The adaptive pipeline is working on implementation only. it makes a miss match between implementation and simulation. If my understanding this issue is correct, how can I prevent from the miss match caused by adaptive pipeline?
Regards
XD

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回答（1 个）

Kiran Kintali
Kiran Kintali 2024-11-19，11:40
Please share your release. Adaptive Pipelining is an optional feature. When enabled it tries to improve timing of your design.
https://www.mathworks.com/help/hdlcoder/ref/adaptivepipelining.html
When enabled all the pipelines inserted by the optimization are properly balanced. If they cannot be balanced for any reasons an error is generated with the error reason in the optimization report.
Please share the release you are experiencing an issue with this feature. Do not hesitate to share your model or contact tech support for assistance.
  2 个评论
xiaodong yu
xiaodong yu 2024-11-20，10:36
Hi,
my release of Matlab is 2023a. the sub module is a complex multiplier:
I use the enable adaptive pipeline for this submodule. it give the compiled module:
In the figure, the delay z^(-d) is z^(-2), the adaptive pipeline added additional delay of 3 delays on the signal validIn, and 3 delay on the muliplier path. This two path are aligned. The submodule as whole, has 3 delay pipeline. How to balance the delay outside the module? instead, I want to keep the total delay of the submodule unchanged when appling adaptive pipeline.
To use distributed pipeline can keep delay of the module unchanged. But I want to use the adaptive pipeline to apply the mult-add module in the compiled module to generate the correct DSP structure for Xilinx FPGA( this is explained in the help page of multiply-add module -algorithms segement).
anyway to solve the dilemma?
Regards
XD
Steven Hatcher
Steven Hatcher 2024-11-20，17:08
For a complex multiplication, there will be 2 sequential multipliers with one being multiply-add. This totals to 5 cycles of latency when Adaptive Pipelining kicks in on them. You need to model with z-5 after the complex multiply and then delay absorption will kick in to leverage the delay block to offset Adaptive Pipelining latency automatically. There's no need to manually add delay blocks on the inputs since Adaptive Pipelining will handle this for you.
Generating code for this subsystem introduces no extra latency as you can see on the valid signal.

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