Implementing logarithmic function via Simulink HDL Coder

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Eirik Nordeng
Eirik Nordeng 2024-3-21
评论： Kiran Kintali 2024-4-12
I need to implement a logarithmic function in Simulink that can be used for generating HDL code using HDL Coder. The Log block in Simulink appears to only support native floating point data types for use with HDL Coder, and an evenly stepped LUT does not provide good enough precision per resources used.
Is there any other preferred way of implementing logarithmic functions in Simulink/HDL Coder?

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Kiran Kintali
Kiran Kintali 2024-3-25
Can you share a bit more about your application and requirements for log?
These results can be generated based on your target chip, latency constraints. I am sharing few sample details for basic log operation in single precision for your review.
>> openExample('hdlcoder/SynthesisBenchmarkOfNativeFloatingPointOperatorsExample')
>> load('hdlcoder_synthesis_benchmark.mat')
>> whos
Name Size Bytes Class Attributes
NFPSynthesisResults 1x1 339902 struct
>> NFPSynthesisResults.Vivado.HardwareDetails
Tool: 'Xilinx Vivado'
ChipFamily: 'Virtex7'
DeviceName: 'xc7v2000t'
PackageName: 'fhg1761'
SpeedValue: '-2'
Version: '2018.3'
>> NFPSynthesisResults.Vivado.MinLatency
Fmax Slices SliceRegs LUTs DSPs RAMs URAMs Latency DataPathDelay Slack LogicLevels LogicDelay RouteDelay
______ ______ _________ _____ ____ ____ _____ _______ _____________ ______ ___________ __________ __________
op_Log 235.29 661 1383 2072 5 0 0 20 4.25 -2.574 14 1.279 2.971
op_Log10 217.86 749 1210 2286 9 0 0 17 4.59 -2.619 15 1.647 2.943
op_Log10_Denorm_on 217.86 749 1210 2286 9 0 0 17 4.59 -2.619 15 1.647 2.943
op_Log2 287.19 667 1022 2054 6 0 0 16 3.482 -2.539 1 3.102 0.38
op_Log_Denorm_on 235.29 661 1383 2072 5 0 0 20 4.25 -2.574 14 1.279 2.971
You can generate more recent results using the instructions in the page.
https://www.mathworks.com/help/hdlcoder/ug/synthesis-benchmark-of-native-floating-point-operators.html
  2 个评论
Eirik Nordeng
Eirik Nordeng 2024-4-2
Details on the application and requirements:
The function is to be implemented for an RTG4 FPGA device (which has distributed Flash configuration cells). The log operation is part of the following function (where log10(PWR_SCALE) = 5.6227):
The output can be limited to ufix10 (saturated at max 1023 and min 0, see figure below), while the input is available as ufix20_En8. The clock rate is fairly low for the given technology and the overall signal update rate is very low. However, I would like to avoid using multicycle constraints if possible.
Herer is a plot showing output for the entire function:
I would like to avoid using an evenly spaced LUT due to the resource consuption for increasing output precision. I am now considering using an iterative method (based on log properties) utilizing shift-adders for implementing the log function by itself, as this has benefits for other projects as well.
Are there any components or examples in Simulink that can help me achieve this or should I start from scratch using basic operators?
Kiran Kintali
Kiran Kintali 2024-4-12
Attaching sample algorithm that could be a starting point for your usecase. You can plugin the algorithm in a MATLAB function block.

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