Hi all,
I have a top subsystem (top_level)
with child subsystems (child_model1, child_model2) in it.
The goal it to verify that internal_signal (the output of child_model1) matches the output of the top level subsystem, no matter what happens to the internal_signal (i.e., I want to compare them).
At this moment I consider using Observer in order to read the internal_signal (as well as the output signal), and using Propery Proving for the requirement: those signals are always the same, no matter what the combination of input signals is. So the content is the following:
However, I get the model incompatible:
Model contains one or more Observer Reference blocks that are not compatible. Simulink Design Verifier can not analyze this model.
Could anyone help me either with the incompatibility or with other ways of such my verification? Thank you in advance.
I also attach my files: the model and observer. I use 2019b version.