How to check into simulink test sequence a local signal into the model

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Claudio Rosso
Claudio Rosso 2024-4-10
编辑： Claudio Rosso 2024-4-12
I would like to check the state of the FSM into a stateflow chart without creating an output variable. And in a similar way some local variables.
I need to check it with verify statement into a test sequence block.
I tried using data store memory and simulink signal but i have problem with red/write consequentially action. I know i could remove that error from model configuration but i want to mantain to be compliant with my workflow.

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