Hi Adithya,
As I understand, you are looking to design a counter that increments every 3 clock cycles within a Xilinx System Generator Subsystem in Simulink.
The Xilinx System Generator Subsystem block allows you to model designs using blocks from both Simulink and Xilinx, and automatically generate integrated HDL code. This setup uses HDL Coder to generate HDL code from Simulink blocks and Xilinx System Generator to generate HDL code from the Xilinx System Generator Subsystem blocks. Here is the link to MathWorks documentation on how to create a Xilinx System Gererator Subsystem:
You can make a counter using two Counters and a Comparator Block in Simulink as follows:
- The output of Comparator block is high when input is above threshold.
- Clock signal block generates a clock signal for logic systems.
- Counter Block counts up or down through a specified range of numbers.
- Set the first counter to count to a maximum value of two. Connect the clock signal output to the increment input of this first counter.
- Then, connect the output of the first counter to a comparator that checks for the value 2.
- Finally, connect the comparator's output to the increment input of the second counter. This configuration ensures that the second counter increments every 3 clock cycles since the first counter will reach 2 after 3 clock cycles, triggering the second counter.
Once your Simulink model is ready, you may refer to the steps mentioned in the MathWorks documentation for HDL Code Generation from Simulink and using Xilinx System Generator for DSP with HDL Coder to generate the HDL code. Here is the link to the documentation:
- https://www.mathworks.com/help/hdlcoder/gs/example-generating-hdl-code-from-a-simulink-model.html
- https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html
I hope this helps!
