Access FPGA External Memory Using AXI Manager over PCI Express Implement

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I tried to follow the example:
I finished generating the bitstream file, programmed it to the board and then restarted.
When I used h = aximanager('Xilinx',' interface','pcie'); command, the following error occurs:
Error using pciexilinx_mex
Error: There is no compatibility FPGA-in-the-Loop device in the system. You may have not installed the driver required for this operation.
Error in hdlverifier.AXIManagerPCIe/openPCIeConnection
Error in hdlverifier.AXIManagerPCIe
Error in aximanager
Later I thought that I did not install the XDMA driver. After I installed it, the problem was still the same. I would like to ask how to solve this?
I implemented it with vivado 2022.2, matlab R2023b, KCU116 fpga board on windows.
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Heman P
Heman P 2024-7-24
From the command window you shared above, I can only observe the "hdlsetuptoolpath".
Could you please verify if the following command (program the FPGA) has been executed before creating an aximanager object?
>> filProgramFPGA('Xilinx Vivado','pcieaximaster.runs\impl_1\pcieAXIMdesign_1.bit',1)

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回答(1 个)

aditi bagora
aditi bagora 2024-5-8
编辑:aditi bagora 2024-5-8
Hello Chia-Cheng,
I understand that you are facing an error while running the example due to a compatibility problem. Often, installing the driver and performing a restart resolves such issues.
However, since you are still facing the same error, there is a possibility that the configuration you have might not be compatible.
Please refer to the provided documentation, which thoroughly outlines the necessary hardware and software specifications.
I hope the information helps in resolving the issue.
  1 个评论
Chia-Cheng
Chia-Cheng 2024-5-8
Thank you for your information. I saw in it that HDL Verifier does not seem to support the FIL of KCU116. I am thinking that this may be the reason for the error. In this case, I wonder if it will not be possible to implement it with this board.

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