FIR filter coeff design for FPGA IP core

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Nikolaos M.
Nikolaos M. 2024-5-8
评论： Nikolaos M. 2024-5-15
Dear All,
I hope this message finds you well. I am currently working on a project involving an Altera DE2-115 board, where I aim to pass stored 32-bit ADC data through a FIR filter. Specifically, I am capturing voice data from a microphone with an 8 kHz sampling rate at 32 bits. I designed a Low Pass filter using MATLAB with the following specifications:
  • Filter Type: Low Pass
  • Window: Hamming
  • Order: 100
  • Sampling Frequency (Fs): 8000 Hz
  • Cutoff Frequency (Fc): 300 Hz
After designing the filter, I exported the coefficients and implemented them in the FIR IP core provided by Altera. However, I encountered an issue where the output is 55 bits instead of the desired 32 bits. I attempted to handle this by truncating the 23 least significant bits, but this resulted in significant noise.
I am seeking advice on how to approach the truncation process effectively. Is there a method or tool available in MATLAB that can assist in determining which bits to remove while minimizing noise?
Thank you.

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Tom Richter
Tom Richter 2024-5-13
Hello Nikolaos,
If I understand correctly, you are only designing the filter in MATLAB and then use Altera IP directly instead of using HDL Coder and DSP HDL Toolbox to generate the IP, right?
First of all, it is normal that there is a bit-growth. However, the input and output dynamic range normally is the same (when gain is 1). That said, you should be able to truncate the MSBs rather than the LSBs.
I would also not suggest using so many bits for input and/coefficients. It would be too expensive with 32 bits and also not desired. The DSPs inside the Altera FPGA should work best with 18bits. The filter should be implemented as a serial filter. With HDL Coder and DSP HDL Toolbox you can do all of that. Find more information here. A good example for a serial implementation can be found here.
The board you are using is already quite old. With release R2024a we stopped supporting the board because we stopped the FPGA Turnkey workflow. Until R2023b you would still be able to use it. This does not mean that you cannot generate code or an IP core with HDL Coder. A MATLAB based FPGA Turnkey example for your board is here. A Simulink based example is this one.
Best regards,
Tom

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