simple IIR filter design

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Safiya 2015-5-5

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https://ww2.mathworks.cn/matlabcentral/answers/215078-simple-iir-filter-design

评论： Stephen23 2015-5-28

Hi, I am using this simple transfer function H(z)= 1/(z^2 + 0.1z+ 0.01), transforming to bilinear. Now I want to generate the VHDL code for this compensator. Not targeting to any FPGA board. but for simple transistor level synthesis like cadence etc. Can I do this using MATLAB. Regards, shayder

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Stephen23 2015-5-28

Here is the text of the original question, just in case Safiya decides to delete the text of this question too (like this one):

Hi, I am using this simple transfer function H(z)= 1/(z^2 + 0.1z+ 0.01), transforming to bilinear. Now I want to generate the VHDL code for this compensator. Not targeting to any FPGA board. but for simple transistor level synthesis like cadence etc. Can I do this using MATLAB. Regards, shayder

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Answer 1

Tim McBrayer 2015-5-5

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You might want to take a look at either HDL Coder or Filter Design HDL Coder to see if either of these products will meet your needs. Both generate cycle-accurate, bit true VHDL or Verilog that is ready for simulation and synthesis.

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Walter Roberson 2015-5-6

HDL Coder and related tools can generate complete descriptions suitable for chip layout programs, and do not need to be targeted to FPGA.

If you want to use floating point then you are going to need a floating point library and it is going to take up a lot of space on your chip.

The recommendation is to avoid floating point and to instead to use the Fixed Point Designer.

Tim McBrayer 2015-5-6

HDL Coder supports many different styles of modeling. The design of your filter is up to you and your requirements.

With HDL Coder, if you need storage for your coefficients--for instance, if you want to change them over time--you can store them in a register implemented with a unit delay. If you want a RAM to store the coefficients, you can do that as well using a HDL RAM block. If you just want a set of fixed coefficients you can specify them with Constant blocks, or as the parameter of a Gain block. If you want to supply the coefficients as external inputs to your filter you can do that as well.

The generated HDL is target-independent unless specifically requested not to be. It can be used for simulation, synthesis (for either FPGA or ASIC), or any other purpose that you would use hand-written HDL for.

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