generated rs code function result is not different with matlab simulink simulation

Question

heo 2024-9-10

回答： Kiran Kintali 2024-9-10

Hello,

I use the rs decoder of hdl coder. the simulation in matlab simulink is correct...

but when I load this code in fpga board and capture data by using the ILA, Its not same...

I think that when generated code is converted to verilog, difference is occured??

possible waring list..

1. optimization option : I set correct clock, fpga board, distributed pipeline ... and so on.

-> I dont know that my setting value is correct????

2. timing satisfy, fpga clock : 16Mhz

3. matlab ver : 23a, vivado ver : 20.2

please give me check point....

thank you your corporation

Je Heo.

Answer 1

Kiran Kintali 2024-9-10

Are you using HDL Coder with this demo and not meeting timing?

openExample('whdl/DecodeAndRecoverMessageFromRSCodewordExample')