why does the module of delay have different data types of input and output?

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ED
ED 2024-9-18
评论： ED 2024-9-19
  1 个评论
ED
ED 2024-9-18
编辑：ED 2024-9-18
But I disable function of reset, it changes into:
Just overlook the different appearance of the delay with and without reset input.
Hasn't this case ever been found by anyone?

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Epsilon
Epsilon 2024-9-18
编辑：Epsilon 2024-9-18
Hi ED,
I tried reproducing this and it seems the unit delay block does indeed produce a 'double' data type signal when used with an external reset. This might be happening due to the initial condition (0.0) being of a ‘double’ datatype in case of the block with external reset. In case where no reset is being used it must be using the definition with the initial value (0) as ‘single’ datatype. The initial conditions change the datatypes for the next iterations. (Note: 0.0 & 0 are just the mentioned values in the parameter dialogue fields and does not represent the datatype of the values)
To get the signal as a 'single' datatype while using an external reset consider using a 'single' datatype value as an initial condition. To do so, directly enter a 'single' datatype value in the initial condition field in the ‘Delay One Step’ block parameters dialogue. Or change the initial condition source from ‘Input’ to ‘Input port’ then attach a 'single' datatype constant to it.
Attaching the resultant image with the implementation.
Hope this helps!

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