It is my understanding that you are trying to generate Verilog code for the ONNX file, and later, planning to deploy it on FPGA boards.
HDL Coder can generate portable, synthesizable Verilog code from MATLAB functions, Simulink models, and Stateflow charts. But currently, the HDL Coder does not support code generation for the function 'importNetworkFromONNX'.
Alternatively, you can create a custom processor configuration and estimate the performance of a pretrained series network. You can then modify parameters of the custom processor configuration and re-estimate the performance. Once you have achieved your performance requirements you can generate a custom bitstream by using the custom processor configuration.
Here, in the following implementation, I have loaded a network from an ONNX file.
% [squeezeNet,ClassNames] = imagePretrainedNetwork("squeezenet");
% exportONNXNetwork(squeezeNet,"squeezeNet.onnx");
net = importNetworkFromONNX("squeezeNet.onnx");
analyzeNetworkForCodegen(net)
You can create, compile, and deploy a 'dlhdl.Workflow' object with the network object by using the Deep Learning HDL Toolbox. Use MATLAB to retrieve the prediction results from the target device. The steps are thoroughly illustrated in the following example:
Additionally, you can refer to the following resources to know more about Custom Deep Learning Processor Generation to Meet Performance Requirements:
