Benefit of non-virtual output port vs. virtual output port in codegen

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John 2024-11-19，8:45

Hi,

Reading through this document, https://www.mathworks.com/help/simulink/ug/ensure-outport-is-virtual.html, my understanding is that for the case of conditional subsystems with a merge block, setting output port to be virtual is a must. Then my questions are

If non-virtual signal results in a hidden Signal Copy block, which will double the memory, what is the benefit of non-virtual signal when using with codegen?
Is my understanding correct that if we have an implementation below with Vector2 is virtual, there won't be additional allocated memory (temporary variable) nor assignment for every element of the vector performed and vice versa for the case of non-virtual?

Thanks,

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