Why do I get errors during compilation of generated systemverilog files when using the Cosimulation Wizard in HDL Verifier R2024a?
I'm trying to generate a cosimulation block for Xcelium. There for I want to use the Cosim Wizard and systemverilog files I generated with the HDL Coder out of my model. I'm following this workflow:
https://www.mathworks.com/help/releases/R2024a/hdlverifier/ug/get-started-simulink-cosimulation-hdl.html
My problem is, that I can't compile the generated sv files inside of the cosimWizard (step "HDL Compilation" inside of the Cosimulation Wizard).
The errors are:
1. xmvlog: *E,NOPBIND (Path) Package my_pck could not be bound
2. xmvlog: *E,ILLPDL (Path) Mixing of ansi & non-ansi style port declarationis not legal
I didn't change the compilation commands and I have already run the "Workflow Adviser" and the "HDL Code Advisor" here everything runs through. I don't use any external sv-files just the ones I generated with the HDL-Coder out of my model.
What can I do to be able to compile the sv-files and generate the cosimulation block?
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