Hi,
To generate custom refernce design for Deep Learning IP Core, first you would need to train the neural network using MATLAB or other MathWorks Toolboxes such as HDL Coder, Deep Learning HDL Toolbox, SoC Blockset.
The following MathWorks documentation provides the steps and examples to prototype deep learning networks on FPGA and SoC devices with custom boards or with custom bitstreams or with custom bitstreams and custom networks.
- https://www.mathworks.com/help/deep-learning-hdl/ug/prototype-deep-learning-networks-on-fpga-and-soc-devices.html
- https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html
- https://www.mathworks.com/help/deep-learning-hdl/ug/generate-custom-bitstream.html
- https://www.mathworks.com/help/deep-learning-hdl/ug/generate-custom-bitstream-to-meet-custom-deep-learning-network-requirements.html
Additionally, you can also explore the following MathWorks documenation top files for HDL IP Core Generation:
- https://www.mathworks.com/help/hdlcoder/hdl-ip-core-generation.html
- https://www.mathworks.com/help/deep-learning-hdl/dlarchitecture.html
- https://www.mathworks.com/help/deep-learning-hdl/deployment.html
To answer your questions regarding "JTAG" and "dlprocessor_0", this block diagram is to show that the "Kintex FPGA" is packed into an "IP" and used as a block which is called "dlprocessor_0". So JTAG will be inside the IP core which you can generate leveraging the above documentation links.
I hope this helps!
