Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project?

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xiaojie
xiaojie 2024-12-29
回答： Kiran Kintali 2024-12-31
hello，everyone！Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project? If possible, what do I need to pay attention to in the user-designed vivado project。

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Arjun
Arjun 2024-12-31
Hi @Xiaojie,
I understand you are asking if it is possible to integrate code generated by HDL Coder into a Xilinx Vivado project.
Yes, you can integrate the HDL code generated by HDL Coder into your Xilinx project. For a more detailed understanding, please refer to the following documentation links.
Once you have the IP Core generated from Simulink then it can be reused in Xilinx Vivado by adding it to the IP Repository:
  • Open your Vivado project.
  • Navigate to Tools > Settings > IP > Repository.
  • Add the path to the directory where your IP core is stored. This makes the IP core available in the Vivado IP Catalog.
In the Vivado IP Catalog, find your IP core and instantiate it into your block design.
I hope this will help!

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Kiran Kintali
Kiran Kintali 2024-12-31
Generating an IP core wrapper for the HDL Coder generated code is the best way to integrate your algorithm into an existing vivado project. You can find the details below. However please note that you can go beyond just IP core and build an entire custom reference design for your board and work within MATLAB enviroment programming and interacting with the board.
https://www.mathworks.com/help/hdlcoder/generate-ip-core-xilinx-soc.html
HDL IP Core Generation
Deploy generated IP core on a target hardware platform
Generate a reusable HDL IP core to design a system that you can deploy on hardware or a combination of hardware and software. Deploy your MATLAB® or Simulink® design:
  • As hardware and software on system-on-chip (SoC) platforms, such as Xilinx® Zynq®, Intel® SoC or Microchip SoC.
  • On standalone FPGA boards, such as an Intel FPGA or a Xilinx FPGA board.
  • On platforms that have a separate FPGA and processor, such as the Simulink Real-Time™ target machine with FPGA I/O boards.
If you are using an SoC platform or a platform that has a separate FPGA and processor, you can partition your design to generate hardware that targets the FPGA fabric and software that runs on the embedded processor of the target platform.
For more details on the workflow, see Targeting FPGA & SoC Hardware Overview. For more details on specific hardware platforms, see HDL Coder Supported Hardware.

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