Changing system Frequency "non-integer value" for OFDM example HDL coder

Question

Vaibhav BHATNAGAR 2025-4-2

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https://ww2.mathworks.cn/matlabcentral/answers/2175913-changing-system-frequency-non-integer-value-for-ofdm-example-hdl-coder

回答： Satwik 2025-7-22

clock_error_HDLCoder.PNG

Hello,

I am trying to generate OFDM IP (VHDL) using HDL coder for a fractional system clock like 62.579MHz (Fsystem) and a sampling frequency of 1.95559375MHz [Fs] (32xFsystem).

Please note due to hardware restriction, I am oblige to use fractional system clock. This is one solution I am trying, my base clock is 51.2MHz.

My IP was working on different system with 62.5MHz clock that is multiple of 125MHz unlike 51.2MHz clock.

In this case: The HDL coder is unable to generate a VHDL code, I get the attached error.

"IP core genratio workflow targeting VHDl language is not supported"

Is this error known?

Thanks in advance for your help.

-BR./

Vaibhav

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Walter Roberson 2025-4-3

The error report is not about frequency problems (those might be a problem later.) The error report is about VHDL not being supported when there is a Model Reference HDL architecture.

Vaibhav BHATNAGAR 2025-4-4