FIL Simulation Failure on Xilinx ZU19EG: "Did not receive version information" Error (MATLAB 2024b + Vivado 2021.2)

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Matthew
Matthew 2025-4-13
评论： Matthew 2025-4-16
Hi MATLAB/HDL Coder community,
I'm encountering a FIL verification failure with ​Xilinx ZU19EG custom board under the following configuration:
  • ​Toolchain:
  • Vivado 2021.2 (WebPACK)
  • MATLAB R2024b (HDL Coder 5.3)
Error Log:
Starting FPGA-in-the-Loop test...
Generating FPGA programming file ...Passed
Programming FPGA ...Passed
Running FIL simulation ...Failed
Error: Did not receive version information from the hardware.
You must have a valid connection, a compatible development board,
and compatible versions of the block and FPGA programming file.
here are some screen shots
I have cross-checked the relevant content in the 'xczu19eg_ffvc1760.bsd' file and the board's circuit schematic, but still cannot identify the issue. The final result is that the bitstream downloads successfully, but the FIL test fails. Is reset mandatory to configure? Or could there be other potential problems?

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回答（1 个）

YP
YP 2025-4-15
The FPGA clock pin could be wrong. Can you share the board manual file?

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