"The FPGA Clock frequency (SampleTime) is set to 128MHz, but the AXI4-Stream to Software clock is set to 200MHz", so the memory clock is faster than the sample production frequency, not slower.
AXI4-Stream to Software block simulates the DMA data transfer between an AXI Stream and a memory. AXI4-Stream to Software block (similar to a real DMA) is buffering multiple sample from the stream and then write those sample together in one burst in the memory.
1) A buffer can contain 1 to N burst (with N being an integer)
2) Burst are written in memory when enough sample has been received from the stream to complete a full burst (or Tlast has been raised). Assuming stream valid is always high, no tlast, no memory contention, no sample format change (bit packing) : burst rate = stream rate / burst size
3)Sample are always "Saved" for next burst by the AXI4-Stream to Software block, unless there is no more buffer available in memory and the burst buffering FIFO is full.
4)Yes, sample are written into the FIFO at the stream rate. if the the FIFO is full, ready signal will go low and any further sample will be discarted until space in the FIFO is available and ready signal go high.
