Hi Erick,
You have used Simulink-generated C++ code in Qspice hierarchical blocks for your buck regulator project. Now, you want to generate Verilog from Simulink, convert it for use in Qspice, and ensure correct I/O mapping between your fixed-point controller and Qspice’s hierarchical block structure. Here’s a step-by-step guide to accomplish this:
1. Generate Verilog Code from Simulink:
- Design your controller in Simulink using blocks to model your fixed-point controller.
- Ensure all data types are compatible with HDL code generation (use Fixed-Point Designer if necessary).
- Open the HDL Coder app in Simulink.
- Select your controller subsystem.
- Set the target language to Verilog.
- Run the HDL Workflow Advisor to produce Verilog code (.v file).
2. Prepare the Qspice Hierarchical Block:
- In Qspice, create a new hierarchical block for your controller.
- Qspice will generate a C/C++ template file for the block, detailing all the I/O ports.
- Compare the generated Qspice block I/O with the Verilog module I/O.
- Take note of any differences in naming, data types, or widths, and plan for any necessary conversions.
3. Integrate Verilog with Qspice:
- Use a tool like Verilator to compile your Verilog code into C++. Verilator is open-source and widely used for this purpose.
- Wrap the generated C++ code in a DLL (Dynamic Link Library), following the structure and I/O mapping specified by the Qspice template. Ensure all signals connect correctly and handle any type conversions (e.g., fixed-point to double).
- Edit the Qspice-generated C/C++ template to instantiate your controller’s C++ class and connect all I/O. Compile this into a DLL and place it in the appropriate directory for Qspice to access.
4. Test and Debug
- Add your new hierarchical block to a Qspice schematic.
- Connect signals and test the simulation.
- Debug any interface mismatches or logic errors.
For more information, refer to the following documentation links:
