Dear all,
I am using SoC Blockset for a simple receiver design for ZCU111 board.
ADC is producing samples with period Ts, these samples go through an FPGA algorithm and are written (stream of samples at the same rate as ADC sample production rate = Ts) to a PS memory using AXI4-Stream to Software block. For some reason, no matter how small processor task duration time is, at some point of time the PS memory is not ready to accept new data (it sets backpressure "ready" signal to low). Of course in this case we have to either drop a sample that cannot be written to the memory or put it to some FIFO (I want the frame to be continuous, have no instant signal phase changes in the read data, so I do not want to drop the sample). When the PS memory is ready to accept the new sample, it sets backpressure "ready" signal to one, and the sample from the FIFO is transferred to the PS memory.
Now, the FIFO will always have at least one element during all further application run. Each time the PS memory will not be ready to accept a new sample, it will be added to the FIFO, and at some point it will also be full (I cannot stop ADC from producing samples, because the signal is continuous and I do not want instant phase shifts to appear in the recorded data), so the design would again drop the samples.
For example, in my model with Number of Buffers = 64, Burst length = 256, FIFO depth = 32, FIFO almost full = 32, Data Width = 128bit, task duration = 1e-4, frame production time = 1e-4 (FrameSize = 25600), starting from 2.35ms "ready" is set to 0 for the first time. This means that after 2.35 seconds from the start of the application, the FIFO in the FPGA logic will already be utilized by at least 1000 samples, in fact much more, and after 20 hours of continuous operation all the internal PL memory will for sure be used, in fact much earlier (I would make task duration and frame size greater as on the real HW but then the simulation would take too much time).
The question is what architecture/blocks to consider to avoid this problem? Or better how to solve the problem of that whatever task duration is set in Task Manager block, and Burst length, Framesize and number of buffers are set in AXi4-Stream to Software block, the PS memory will assign 0 to "ready" signal at some point of time, causing FIFO to rapidly become full in case no samples are dropped?
Thank you for your answers!
