HDL generated code and testbench does not pass Xcelium sim

Question

0 个投票

I am using the testbench generated out of HDL coder to run a sim of the device under test (HDL gen) in Xcelium. I am getting LSB mismatches for some samples. Aren't the expected test vectors generated in Simulink bit-exact?

3 个评论
显示 1更早的评论隐藏 1更早的评论

Torsten 2026-9-13，11:33

编辑：Torsten 2026-9-13，11:50

Answer from AI:

Yes, the expected test vectors generated by Simulink are bit-exact relative to the Simulink simulation, but only under specific configuration alignments. If you are seeing Least Significant Bit (LSB) mismatches in Cadence Xcelium, it usually points to a subtle structural discrepancy between how Simulink mathematically handles a operation and how the synthesized RTL handles it. [1, 2]

Common Causes for LSB Mismatches

1. Accumulator and Multiplier Internal Precision

The Issue: Look closely at math blocks (like Product, Gain, or Discrete-Time Integrator). If their internal calculations use different rounding modes or bit-growth settings than what the RTL implements, LSB discrepancies will leak into your output .dat files. [1, 2]
The Fix: Open your block parameters, navigate to the Data Types tab, and ensure the Output data type and any internal intermediate data types are explicitly set to matched Fixed-point configurations (fixdt(...)) rather than inheriting types dynamically.

2. Mismatched Rounding and Overflow Modes

The Issue: Simulink blocks default to rounding modes like Floor or Nearest, and overflow modes like Wrap or Saturate. If you change these settings in a block but your global HDL Coder generation settings use optimization flags that replace these blocks with native hardware primitives (which often default to Floor and Wrap), you will get LSB mismatches.
The Fix: Ensure that the block-level settings for Rounding mode match what your target hardware architecture supports, or disable aggressive HDL optimizations that bypass these constraints.

3. Optimizations (Floating-Point to Fixed-Point Conversion)

The Issue: If your model relies on the MathWorks Fixed-Point Designer or Native Floating-Point architectures, slight precision variances can occur. Certain automated optimizations, such as pipelining, resource sharing, or altering loop unrolling structures, change the order of operations. In fixed-point math, changing the order of operations changes the rounding effects on the LSB.
The Fix: Temporarily disable options like Adaptive Pipelining or Resource Sharing in the HDL Coder Workflow Advisor to see if the LSB errors vanish. If they do, the mismatch is caused by operation reordering.

4. Clock Enable and Reset Latency

The Issue: In Cadence Xcelium, data signals must align perfectly with the target clock edges. A common bug occurs if the initial reset sequence in the simulator shifts the actual RTL pipeline behavior by just half a cycle or a full cycle relative to the captured .dat vectors. This looks like a stream of bad samples or LSB drift.
The Fix: Look at the generated testbench code and verify that the Hold Time or Setup Time configuration matches your simulator's time resolution precision. [1, 2, 3]

How to Diagnose and Resolve the Issue

Isolate the Sample: Check your Xcelium console logs to identify whether the LSB mismatch is a constant offset (e.g., always off by 1) or if it only happens on specific mathematical transitions (like when an accumulator rolls over).
Review the Testbench Data: Open the generated .dat files (found in your hdlsrc directory) to verify the exact bit patterns Simulink recorded.
Use Cosimulation: Instead of relying strictly on static file-based testbenches, use HDL Verifier Cosimulation. Running Xcelium side-by-side with Simulink using a cosimulation block allows you to probe internal signals interactively to pinpoint exactly which block introduces the LSB variance.

If this doesn't help, contact support:

https://uk.mathworks.com/support/contact_us.html

Sumit about 13 hours 前

移动：Torsten about 11 hours 前

Thank you very much for the detailed response. I will try out your suggestions. In my view this is a bug that needs to be fixed by Mathworks. When the HDL is generated along with the associated test bench, it should guarantee complete bit exact matching between the HDL coder generated expected samples and Xcelium generated samples regardless of the various settings. Do you agree with that view?

Torsten about 11 hours 前

Answer from AI:

While it is frustrating when an out-of-the-box test bench fails, a "guaranteed match regardless of settings" is structurally impossible. This mismatch typically stems from differences in how Simulink's floating-point simulation engine handles intermediate mathematical operations versus how fixed-point HDL calculates them, or how the HDL simulator interprets timing and initial states.

Before submitting a bug report to MathWorks, check the most common configuration culprits causing LSB drift:

1. Intermediate Precision & Accumulator Sizes

Simulink often computes block operations using double-precision math internally before casting the final result back to your specified fixed-point type. The generated HDL, however, must execute these operations using actual bit-widths.

The Fix: Review blocks like Product, Gain, or Sum. Ensure that your Output data type and Accumulator data type are explicitly defined as fixed-point rather than inheriting "Same as input". If the accumulator wraps or truncates differently in the hardware description than it does in Simulink's ideal mathematical interpretation, you will see a 1-LSB variance.

2. Rounding Mode Mismatches

If your model relies on rounding (e.g., Nearest, Convergent), ensure the target HDL handles these boundary conditions identically. A value exactly halfway between two integers might round up in Simulink but truncate or round down depending on how the HDL compiler optimizes the logic.

The Fix: If absolute bit-exactness is a strict requirement, switch the rounding mode to Floor (Truncation) across your DUT. Floor rounding requires no extra hardware logic and behaves identically in both simulation environments.

3. Optimization Discrepancies (Pipelining & Delay Balancing)

If you have settings like Adaptive Pipelining, Clock Rate Pipelining, or Floating-Point Libraries enabled in HDL Coder, the code generator restructures the logic to meet timing.

The Fix: If pipelining is enabled, ensure Delay Balancing is also turned on. If the latency of the HDL design does not perfectly match the expected latency recorded in the .dat files, the test bench will compare sample \(N\) from Simulink against sample in Xcelium, which manifests as massive or intermittent LSB mismatches. [1]

4. Xcelium Initialization States (X-Optimizations)

Simulink initializes all signals to rigid defaults (usually 0). Xcelium and other digital simulators may evaluate uninitialized registers or reset sequences as X (unknown) or hold transient values for a fraction of a delta cycle.

The Fix: Make sure your test bench reset duration is long enough to completely flush the pipeline. Check if the LSB mismatches occur only during the first few dozen samples or if they persist throughout the entire simulation run.

Next Steps for Verification

To isolate whether this is an HDL Coder bug or a configuration issue, try running an HDL Cosimulation or a FPGAs-in-the-Loop (FIL) test using HDL Verifier. If the cosimulation matches perfectly but the standalone Xcelium test bench fails, the issue is likely due to file I/O formatting or clock/reset timing in the generated script wrapper.

请先登录，再进行评论。

请先登录，再回答此问题。

请先登录再关注