Problem with the design verifier Simulink

Question

Nedra Ebdelli 2015-6-1

0
链接

此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/221892-problem-with-the-design-verifier-simulink

评论： Nedra Ebdelli 2015-6-2

I want to exract counter examples from my model but an error has encoured that I didn't understand it.

Model "model" is set to import initial state data from the matlab workspace.Simulink Design Verifier does not support this configuration.You must uncheck the initial state in the load from workspace area of the Data.
Simulink Design Verifier failed to initialize: is incompatible with simulink Design Verifier.

The problem that mymodel doesn't contain a block from workspace or from File. Please I need a help.

0 个评论
显示 -2更早的评论隐藏 -2更早的评论

请先登录，再进行评论。

请先登录，再回答此问题。

Answer 1

Sebastian Castro 2015-6-2

0
链接

此回答的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/221892-problem-with-the-design-verifier-simulink#answer_181244

If you go to Simulation > Model Configuration Parameters, then go to the Data Import/Export section, there should be an "Initial State" checkbox (2nd option in that menu).

Unchecking that should get rid of the issue -- assuming you don't need to use that option for other simulations.

- Sebastian