If you have a data value that isn't originally zero, but becomes zero when quantized to fixed point, you could get this message. If you have a persistent variable feeding the divide, and the persistent value has an initial value of zero, that could be another possible cause.
Perhaps something like this might work:
if b ~= 0
c = a/b;
else
c = <max value for c's data type>;
end
The larger issue is that you have some source code that is resulting in a division. In general, division with an arbitrary denominator is not supported for HDL Synthesis. Even if your tool can synthesize it, it will take a lot of FPGA real estate.
