Simulink HDL Coder - Filter - Fully Serial Interfacing

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Jast
Jast 2015-9-18
编辑： Jast 2015-9-18
I have generated an IIR filter using FDAtool, ported it to simulink, and got it running on an FPGA in full parallel mode. Now I want to implement the fully serial architecture, but I cannot find an example timing diagram for interfacing with the top level entity of the filter. Does anyone know where to find such an example timing diagram which explains how to interface with the fully serial filter?
Thanks

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Bharath Venkataraman
编辑：Bharath Venkataraman 2015-9-18
There is no timing diagram readily available, but if you look at the HDL code, you will see the interface is to provide a clock input that is N times faster (the setting for N is displayed during HDL code generation: Clock Rate is N times the sample rate for this architecture) and feed in the data/samples at 1/N the clock rate.
You can also generate a testbench for the design, which will show how to do this in HDL.

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Jast
Jast 2015-9-18
编辑：Jast 2015-9-18
Thanks for the answer.
It seems to be indeed that way, the clock should be N times faster than the sample clock, and then it works. It actually gives very nice results. I implemented a 4th order chebychev type one IIR filter on a cyclone V, with 16 bits coefficients, 16 bit inputs, and 32 bits internal representation. It uses 2 mulitipliers in my device, with a samplerate of 4.5 MHz, and a clock of 58.5MHz for the IIR filter. The filter performs almost identical to the floating point version, so that is very nice indeed. It performs identical to the fully parallel version, wich is reassuring
HDL coder should be configured properly so that pipeline registers are inserted (but this concerns the full parallel version more of course), otherwise Fmax becomes inacceptible low.
I'll have a look at the testbench generation as well
Cheers

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