Black box in system generator
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im implementing an "and" gate in system generator using black box, i have coded the "and" gate in vhdl, i have called the block in black box , my a,b,c are all "std_logic" only, i have given fix_1_0 as gateway input to the black box with constant simulink block, but im nt able to simulate the logic in simulator, its nt showing any simulation error, nothing ,kindly help me !!!
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2015-11-19
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2023-2-2
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