Problems with the HDL Workflow Advisor

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Nikolas Grotz
Nikolas Grotz 2015-12-15
回答： Varun Bhaskar 2015-12-17
Hi,
i am trying to convert a MATLAB function into VHDL code with the HDL workflow advisor and i want to verify it with the FPGA-in-the-loop. With a simple function and testbench (see attachement function1 below) it works but with little changes (see attachement function2 below) my computer hangs or crashes during "Verify with FPGA-in-the-loop" at the point "Running programmable file generation..." and there are no error messages.
I think both should work because the functions are very simple. Anybody an idea?
best regards Niko

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回答（1 个）

Varun Bhaskar
Varun Bhaskar 2015-12-17
Hi,
Please reach out to Technical Support and they should be able to assist you by creating a case. Kindly provide them with the project file too.

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