How can adder configuration be modified in Discrete FIR Filter (DSP System Toolbox HDL Coder Support)?

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The Discrete FIR Filter defaults to a linear adder architecture with no pipelining, leading to large propagation delays. Is there a way to modify the architecture to implement an adder tree with pipelining?

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Rohit Jain
Rohit Jain 2016-3-1

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