stateflow Can't figure out a simple transition

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Using stateflow with R2015b
I come from a vhdl backgroud. I am trying to convert this code
case state is
when WAIT_FOR_DSP =>
if(dataLatchEn == '1') then
b <= '1';
state <= RF_ON_WAIT_FOR_ACK;
end if;
when RF_ON_WAIT_FOR_ACK =>
b <= '0';
if(ackReceived = '1') then
state <= WAIT_FOR_DSP;
end if;
end case;
to stateflow. This is what I got
b is never getting set to 1 and I think that the transition is taking priority over the state execution since both are testing for dataLatchEnIn being true.
In that case I am at a loss how to code the above vhdl code into stateflow properly.
I guess I can add additional state to perform the b <= '1'; but I don't want to do that.
Thanks for the help, Amish
  1 个评论
Amish Rughoonundon
Amish Rughoonundon 2016-3-17
Found the fix. You have to use en, du, exit: before the if so that at any time, the if statement is processed.

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Amish Rughoonundon
Amish Rughoonundon 2016-3-17
Found the fix. You have to use en, du, exit: before the if so that at any time, the if statement is processed.

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