16 bit input output parameter generation using HDLCoder
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Hello all,
I'm using HDL Coder tool to generate Verilog modules for FPGA implementation. My design is a Adaptive Predictor for Speech Signal. I see that HDL Coder always generates a 14-bit input & output parameters. Is there a way by which I can generate 16-bit signals?
Thank you,
Shruthi Sampathkumar.
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Tim McBrayer
2016-4-5
1 个投票
HDL Coder allows you to choose the default word length to suggest during fixed-point conversion. This is settable on the "Fixed-Point Conversion" tab in the Workflow Advisor, when you have selected "Propose fraction lengths". You can also choose a fixed fraction and let the tool choose the word length.
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