HDL Workflow Advisor and Xilinx System Generator
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Hi everyone,
I am working on generating an IP Core Generation using HDL coder for some blocks designed in System Generator, but I have an error when I use HDL Workflow Advisor.
The message shows in stage 2.3 Check Block Compatibility:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/153888/image.gif)
Thanks in advance for your help.
BR,
Romel
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